Glass-Core Substrates Market Outlook 2026–2036: Market Size, Growth Drivers, Key Players, Strategic Developments & Adoption Forecast for Glass-Core and Glass-Interposer Packaging, Panel-Level Processing and Chiplet Integration for AI Accelerators — A Meticulous Next™ Foresight Brief

This Meticulous Next™ brief examines how glass — as a core material replacing organic laminates in chip substrates, and as a panel replacing the silicon interposer — will change how the largest chips are packaged over the next 5–10 years. The AI accelerator has outgrown its packaging. Organic substrates warp as packages pass 100 millimetres on a side, their fine wiring and flat surfaces limit how many chiplets and memory stacks can be placed together, and the silicon interposers that connect them are made on round wafers in a process that has been the tightest bottleneck in AI hardware supply. Glass is flat, stiff, stable with temperature, able to carry far denser through-vias and wiring, and made in large rectangular panels. Intel announced its glass substrate programme in September 2023; Samsung Electro-Mechanics, SKC's Absolics, LG Innotek and others have pilot lines and samples with customers; qualification programmes have begun with AMD and others; and the industry expects first products in 2027 to 2028 with mass production between 2027 and 2030. The brief maps the technology, its indicative market size and forecast, the factors behind its growth, the developments of the last 24 months, the key players operating in the space and the adoption trajectory to 2036.

It is a focused 28-page decision brief for chip designers and hyperscalers, foundries and outsourced assembly and test providers, substrate and interposer makers, glass and materials suppliers, equipment makers for through-glass vias and panel processing, and investors. It presents an indicative trajectory rather than a segmented market model. Its purpose is to identify when glass cores and glass panels reach production, which supply chains form, and who captures the resulting value.

A chip package has two layers that glass can replace. The substrate is the laminated board that connects the chip to the circuit board; today its core is an organic resin reinforced with glass fibre, which warps, absorbs moisture and limits wiring density as packages grow. A glass core keeps the same construction but replaces the organic core with a sheet of glass carrying through-glass vias, which gives a flatter, stiffer, more stable base with ten times the via density and allows packages above 100 millimetres on a side. The interposer is the fine-wired layer that connects chiplets and high-bandwidth memory stacks on top of the substrate; today it is silicon, made on 300-millimetre wafers in processes such as TSMC's CoWoS whose capacity has constrained AI accelerator supply. A glass interposer or a glass panel-level package does the same job on large rectangular panels at lower cost per area and with more room for chiplets and memory.

Glass is not a drop-in. Through-glass vias must be formed by laser and etch at millions per panel without cracking the glass; copper must adhere to glass; the glass must survive assembly stresses and thermal cycling; and panel-level lines need new handling, lithography and inspection equipment. These are the problems the pilot lines are solving. Absolics produced mass-production samples at its Georgia plant in 2025 and started qualification with major customers including AMD, targeting commercialization in 2026. Samsung Electro-Mechanics runs a pilot line at Sejong, supplied samples in 2025 and plans a glass-core joint venture with Sumitomo Chemical in 2026. LG Innotek built a pilot line at Gumi and is developing prototypes with large technology companies. Intel, TSMC and Rapidus target mass production between 2027 and 2030, and the industry expects first products in 2027 to 2028.

The demand comes from the AI accelerator roadmap. Each generation adds chiplets, memory stacks and package area, and each needs more wiring between them; organic cores and silicon interposers are reaching limits of warpage, size and supply. The packaging bottleneck has become a strategic issue for hyperscalers, chip designers and governments: the Absolics plant in Covington, Georgia, was built with about USD 600 million of investment and support from the U.S. CHIPS programme, and Korea's substrate makers are positioning glass as the next step after the flip-chip substrates they already lead. Glass cores enter first in the largest and most valuable packages, where the cost of the substrate is small against the cost of the chips it carries.

The glass-core substrate market — glass-core substrates, glass interposers, glass panels and the through-glass-via and panel-processing equipment sold for chip packaging, including qualification and pilot-line volumes — is estimated at USD 0.15–0.3 billion in 2026, consisting of pilot-line equipment, packaging-grade glass and qualification volumes. Meticulous Next™ expects it to reach USD 8–12 billion by 2036, an indicative CAGR of 45–50% from a small base, as glass cores enter AI accelerators and high-performance processors from 2027 to 2028, reach volume at multiple suppliers around 2030 and extend to panel-level interposers and broader high-end packaging in the early 2030s. Growth is gated by qualification at AMD, Intel, Nvidia-class customers and at foundries and assemblers, by through-glass-via yield at volume, and by equipment availability. The mix shifts from equipment and pilot volumes toward substrates and interposers at scale. South Korea and the United States lead on substrate pilot lines; Taiwan and Japan lead on foundry packaging and glass supply; the United States funds domestic capacity.

The base case assumes first glass-core products ship in 2027 to 2028 and volume production at multiple suppliers arrives around 2030. An accelerated case adds an early adoption decision by a leading AI accelerator designer and fast through-glass-via yield gains, bringing the inflection to 2029 and lifting the 2036 value to the top of the range. A delayed case assumes cracking, adhesion or yield problems at volume, or organic and silicon incumbents extend their limits, pushing the inflection to 2032 and keeping glass in a small number of flagship packages.

Growth drivers

• AI accelerator packages are passing 100 millimetres on a side with more chiplets and memory stacks each generation, beyond what organic cores can hold flat.
• Silicon interposer capacity has been the tightest constraint on AI hardware supply, and glass panels offer a larger, cheaper alternative surface.
• Glass carries far denser through-vias and finer wiring, which the chiplet roadmap requires.
• Governments and hyperscalers treat advanced packaging as strategic, funding domestic glass-substrate capacity.

Enablers

• Pilot lines with mass-production samples at Absolics, Samsung Electro-Mechanics and LG Innotek and qualification with customers including AMD.
• Through-glass-via laser-and-etch processes and copper adhesion solutions reaching volume yield.
• Panel-level lithography, handling and inspection equipment from established and new vendors.
• Packaging-grade glass from Corning, AGC, Schott and NEG.

Restraints and barriers

• Through-glass-via yield, cracking and copper adhesion at millions of vias per panel are unproven at volume.
• Qualification cycles at chip designers, foundries and assemblers take years and decide who ships first.
• Equipment for panel-level glass processing is new and available from few vendors.
• Organic substrates and silicon interposers keep improving and hold the installed base.

Five converging forces will determine how fast, and how far, glass replaces organic cores and silicon interposers: (1) the size and density demands of the AI accelerator roadmap; (2) through-glass-via yield and reliability at volume; (3) customer qualification at AMD, Intel, Nvidia-class designers and at foundries and assemblers; (4) panel-processing equipment and glass supply; and (5) government and hyperscaler funding for domestic packaging capacity. The brief assesses each force for direction, speed and confidence.

The key players operating in glass-core substrates and glass packaging include Intel Corporation, Samsung Electro-Mechanics Co., Ltd., Absolics Inc. (SKC Co., Ltd.), LG Innotek Co., Ltd., Taiwan Semiconductor Manufacturing Company Limited, Rapidus Corporation, Advanced Micro Devices, Inc., NVIDIA Corporation, Broadcom Inc., Corning Incorporated, AGC Inc., SCHOTT AG, Nippon Electric Glass Co., Ltd., Sumitomo Chemical Co., Ltd., Ibiden Co., Ltd., Unimicron Technology Corporation, Shinko Electric Industries Co., Ltd., Kinsus Interconnect Technology Corp., Toppan Holdings Inc., Dai Nippon Printing Co., Ltd., ASE Technology Holding Co., Ltd., Amkor Technology, Inc., Applied Materials, Inc., LPKF Laser & Electronics SE, Onto Innovation Inc., Manz AG, Plan Optik AG, Georgia Tech Packaging Research Center, Ajinomoto Fine-Techno Co., Inc. and 3D Glass Solutions Inc. The brief profiles representative players in each archetype and assesses which are positioned to supply glass packaging at volume.

The competitive landscape is forming around six archetypes. Glass-core substrate makers run pilot lines and qualify with customers. Integrated device makers and foundries develop glass packaging within their own process roadmaps. Chip designers and hyperscalers qualify and specify glass for their largest packages. Glass and materials suppliers provide packaging-grade panels, build-up films and adhesion chemistry. Equipment makers supply through-glass-via formation, panel lithography, handling and inspection. Assemblers and research centres integrate and test. Competitive intensity is moderate in 2026 and is expected to rise as first products ship in 2027 to 2028 and Taiwanese and Japanese substrate makers enter.

Where value migrates.

In 2026 value sits in pilot-line equipment, packaging-grade glass and qualification volumes. By 2030 it moves to glass-core substrates in volume for AI accelerators and high-performance processors, panel-level glass packaging at foundries and assemblers, and through-glass-via and panel equipment at multiple vendors. By 2036 it settles in substrate makers that qualified first and scaled, glass suppliers with packaging-grade capacity, equipment makers for vias and panels, and the chip designers and hyperscalers whose largest packages depend on glass. Substrate makers that stay on organic cores lose the high-end; equipment makers without panel-level tools miss the capex cycle.

Capital is concentrating in glass-core pilot lines and plants — the Absolics plant in Georgia at about USD 600 million with CHIPS support, Samsung Electro-Mechanics' Sejong line and planned joint venture with Sumitomo Chemical, and LG Innotek's Gumi line — and in through-glass-via and panel equipment. Chip designers and hyperscalers fund qualification; Intel, TSMC and Rapidus fund glass packaging within process roadmaps. Patent activity is concentrated in through-glass-via formation, copper adhesion on glass, panel warpage control, glass compositions and panel-level lithography. The brief tracks four indicators: customer qualifications completed, first glass-core products shipped, through-glass-via yield at volume, and panel-level glass packaging qualified at a leading foundry or assembler.

South Korea leads on glass-core substrate pilot lines through Samsung Electro-Mechanics, Absolics' parent SKC and LG Innotek, with government support. The United States hosts the first commercial glass-substrate plant at Absolics in Georgia, Intel's programme and the hyperscaler and chip-designer customers. Taiwan and Japan lead on foundry packaging through TSMC and Rapidus and on glass and materials through AGC, Nippon Electric Glass, Sumitomo Chemical and Ajinomoto Fine-Techno; Corning and SCHOTT supply from the United States and Europe.