Panel-level fan-out packaging lines Market Outlook 2026–2035: Growth Drivers, Key Companies, Strategic Developments & Adoption Forecast — A Meticulous Next™ Foresight Brief

This Meticulous Next™ brief examines panel-level packaging, meaning the packaging of chips on rectangular panels instead of round wafers, so that more packages are processed in each pass and large AI packages fit with less waste. It tests how far panel-level fan-out lines can move from pilots to volume production by 2035.

Panel area is the first argument. A 310 mm by 310 mm panel offers about 96,100 mm² of usable area against about 70,700 mm² for a 300 mm wafer, roughly 1.4 times as much, and the larger panel of about 510 mm by 515 mm reported for TSMC mass production offers about 262,650 mm², roughly 3.7 times a wafer. The conclusion is that panels cut the cost per package most for large packages, which is the direction AI accelerators are taking.

Lines are now being built. ASE announced an automated 310 mm by 310 mm panel-level line on 28 May 2026 for AI, high-performance computing and chiplet packages, with line and space of 2 µm for FOCoS and 8 µm for FOCoS-Bridge and production targeted for the first half of 2027. The conclusion is that a leading packaging provider is moving from development to a production schedule, ahead of the foundries.

Foundries and chipmakers are moving in the same direction. TSMC is reported to be building a pilot line for its CoPoS platform at its AP7 campus in Chiayi with large scale output reported from 2027 and a fuller ramp in 2028 and 2029, and Samsung Electronics already applies panel-level packaging to mobile processors and power management chips and plans to extend it to AI chips. The conclusion is that panel-level packaging is broadening from mobile and power parts to AI parts, which sets the volume for line makers and material suppliers.

The brief treats panel-level fan-out packaging as an accelerating signal with a nine year horizon to 2035. It identifies which panel formats and companies move first and what each means for packaging firms, foundries and equipment suppliers. It is a focused 103-page decision brief that presents an indicative trajectory rather than a segmented market model.

In wafer-level fan-out packaging, chips are placed on a round carrier, covered in mold compound and connected through redistribution layers. Panel-level packaging does the same on a rectangular panel, so more packages fit on each carrier and large packages waste less edge area. Panels are processed on lines that handle panels of 310 mm and above, and most lines today are small and run for mobile and power chips.

Cost per package is the main reason to move. Panel area grows quickly with format, with a 310 mm panel offering about 1.4 times the area of a 300 mm wafer and a 510 mm by 515 mm panel about 3.7 times, so the same line steps produce more packages. The conclusion is that the case for panels strengthens as packages grow, and the case is weakest for small packages that already fit well on wafers.

Line makers are adding precision. ASE states line and space of 2 µm for its FOCoS platform and 8 µm for FOCoS-Bridge on its 310 mm line, which covers both direct redistribution layers and bridge-based packages. The conclusion is that panel lines are aiming at the same package types as wafer lines, and the choice between them will turn on yield rather than on capability.

Glass panels are the next format. Rapidus is reported to be developing glass-based panel-level packaging on 600 mm by 600 mm panels with a target of 2028, and Intel showed a package with a glass core in January 2026 and places commercial deployment in the second half of the decade. The conclusion is that large glass panels arrive after the 310 mm lines and extend the growth path beyond 2030.

The limits are panel warpage and handling, yield at fine line and space, gaps in equipment and process standards and the capital needed for new lines. The brief tests each limit against the cost trajectory to 2035.

The panel-level packaging market, covering fan-out and chip-on-panel packaging services processed on panels of 300 mm or larger for processors, accelerators and power and mobile chips, and excluding wafer-level fan-out on round wafers, substrate manufacturing, packaging equipment and materials sold separately, and display panel production, is valued at USD 0.8–1.3 billion in 2026 and is projected to reach USD 5.96–9.69 billion by 2035, at a CAGR of 25%.

The 2026 base rests on packaging services processed on panels of 300 mm and above, mainly in Taiwan, South Korea, China and Japan. Growth then follows AI package size, the move of foundries to large panel formats and the spread of automated lines.

The forecast is sensitive to panel yield, the timing of foundry volume production and the pace at which glass panels qualify.

Scenarios.

The base case assumes 310 mm lines reach production in 2027 and a leading foundry ramps a large panel format from 2028, bringing the inflection to about 2029 and a 2035 value near the middle of the range. An accelerated case assumes panel yields match wafer yields by 2028 and glass panels qualify early, bringing the inflection to 2027 and lifting the 2035 value to the top of the range. A delayed case assumes warpage and yield problems keep panels to small packages, moving the inflection to 2032 and holding growth at the bottom of the range.

Growth drivers

• AI accelerator package growth.
• Cost per package.
• Panel area utilisation.
• Power and mobile chip volumes.

Enablers

• Packaging and foundry partnerships.
• Finer line and space processes.
• Public incentives.
• Automated panel lines.

Restraints and barriers

• Panel warpage and yield.
• Equipment and standards gaps.
• Capital intensity.
• Skills.

The direction of panel-level packaging is set by package size growth, cost per package, panel area use, equipment readiness and the capital spent on packaging lines.

The key participants in panel-level fan-out packaging include ASE Technology Holding Co., Ltd., Powertech Technology Inc., Samsung Electronics Co., Ltd., Samsung Electro-Mechanics Co., Ltd., Taiwan Semiconductor Manufacturing Company Limited, Intel Corporation, Amkor Technology, Inc., JCET Group Co., Ltd., Innolux Corporation, Nepes Corporation, Rapidus Corporation, SKC Co., Ltd., AUO Corporation, Corning Incorporated, Applied Materials, Inc., Disco Corporation, Ajinomoto Co., Inc., Onto Innovation Inc., ASMPT Limited, Camtek Ltd., NVIDIA Corporation, Advanced Micro Devices, Inc., Broadcom Inc., Qualcomm Incorporated, MediaTek Inc., Apple Inc., SK hynix Inc., Micron Technology, Inc., Infineon Technologies AG, STMicroelectronics N.V., NXP Semiconductors N.V., Texas Instruments Incorporated, Tokyo Electron Limited, KLA Corporation, Lam Research Corporation, Ibiden Co., Ltd., Unimicron Technology Corp., imec, Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. and SEMI.

The brief profiles representative participants in each archetype and assesses which are positioned to lead as panel formats grow.

ASE, Powertech Technology, Amkor Technology, JCET and Nepes lead among packaging providers, Taiwan Semiconductor Manufacturing, Samsung Electronics, Intel and Rapidus among foundries and chipmakers, and Applied Materials, Disco, Onto Innovation, ASMPT and Camtek among equipment suppliers. Competitive intensity is moderate in packaging, where few firms run panel lines, and rising as foundries enter.

Where value migrates.

In 2026 value sits with packaging providers running small panel lines and with equipment suppliers selling pilot tools, because few lines exist and each tool is qualified for the first time. By 2029 it moves toward foundries and large panel formats as AI packages grow and cost per package falls. By 2035 it settles with high-yield panel lines at scale, where process control and material supply set the margin. Margins hold for suppliers with qualified tools and high panel yield, and narrow for providers of standard packages that wafers also serve.

The signals converge on a market that is moving from pilots to production schedules. An automated 310 mm line with a 2027 target, a reported foundry pilot line and glass panel programmes support growth, while warpage, yield and the lack of equipment standards hold back adoption.

Structural limits show where progress could slow: yield at fine line and space, the handling of large panels, the pace of glass panel qualification and the capital needed per line. The brief therefore tracks four indicators: panel lines in production, panel yields, packages shipped on panels and glass panel pilot orders.

Pilot and 310 mm lines first, then large foundry panel formats, then glass panels is the expected order of change.