Scale-up interconnects Market Outlook 2026–2034: Growth Drivers, Key Companies, Strategic Developments & Adoption Forecast — A Meticulous Next™ Foresight Brief

This Meticulous Next™ brief examines scale-up interconnects, the fast links that join AI accelerators inside a rack or pod so that they act as one large processor. It tests how far open standards such as UALink and scale-up Ethernet take share from proprietary rack fabrics by 2034, and what that means for chipmakers, switch vendors, hyperscalers and the suppliers of interface technology.

The open alternative has a specification. The UALink Consortium published the final UALink 1.0 specification on 8 April 2025, with 200 GT/s per lane, links of one, two or four lanes reaching 800 GT/s in each direction, support for up to 1,024 accelerators in one system, round trip latency under one microsecond and a physical layer built on standard Ethernet components. The conclusion is that an open fabric now exists on paper at the scale of the largest racks, and members can begin chip design.

The proprietary fabric sets the benchmark. NVIDIA NVLink connects 72 GPUs in one Blackwell NVL72 rack and reaches 1.8 TB/s per GPU in its fifth generation, with a sixth generation projected near 2.4 TB/s for Vera Rubin, and NVIDIA plans larger racks in 2026 and 2027. The conclusion is that open fabrics must match a moving target, and the gap in bandwidth and in software support decides how fast buyers consider alternatives.

Ethernet is a second open route. Broadcom contributed the Scale-Up Ethernet framework to the Open Compute Project, and version 1.0 was released on 5 September 2025, while the ESUN workstream launched at the OCP Global Summit in 2025 and coordinates with IEEE 802.3 and the Ultra Ethernet Consortium. The conclusion is that data centre operators can choose between a purpose built fabric and an Ethernet based one, which gives switch vendors a path to enter the rack.

Products are approaching. AMD disclosed about 3.6 TB/s of scale-up bandwidth per accelerator for the MI455X at CES in January 2026, and its Helios rack with UALink silicon was reported in qualification at select hyperscalers by mid 2026, with wider availability dependent on vendor roadmaps into 2027. The conclusion is that the first open fabric racks arrive only a little after the next proprietary generation, so the test is volume, not specification.

The brief treats scale-up interconnects as a high-impact signal with an eight year horizon to 2034. It identifies which chipmakers, switch vendors and interface suppliers capture value as rack scale systems become the unit of AI computing. It is a focused 106-page decision brief that presents an indicative trajectory rather than a segmented market model.

Scale-up links are different from the network between racks. A scale-up fabric lets accelerators read and write each other memory directly at very high bandwidth and low delay, so that a large model can be split across many chips as if they were one. The conclusion is that the size of the scale-up domain limits the size of the model that can run efficiently, which makes the fabric a central part of AI system design.

UALink builds on Ethernet technology but not its protocol. Its physical layer uses standard 200 Gb/s Ethernet signalling, while its transaction layer gives up to 95% protocol efficiency, with UALinkSec for encryption and Virtual Pod partitions for multi-tenant use. The conclusion is that suppliers can reuse existing high speed circuit designs, which shortens development, while the protocol is tuned for memory style traffic.

Ethernet based scale-up takes another route. Scale-Up Ethernet and the ESUN work extend Ethernet with the delay and reliability needed inside a rack, and the Synopsys 224G PHY supports up to 1.6T Ethernet and UALink 200G signalling. The conclusion is that the same physical circuits can serve both standards, so suppliers of interface technology gain from either outcome.

The competitor is ahead on software. NVLink is supported by the software stack and the racks that NVIDIA already ships, and NVLink Fusion extends access to other chip makers. The conclusion is that the open fabrics need accelerators, switches and software that work together at the start, and the first hyperscalers that qualify them will set the pace.

The limits are the lag behind proprietary bandwidth, the lack of switch silicon in volume and the cost of qualifying a new fabric. The brief tests each limit against the evidence to 2034.

The scale-up interconnects market, covering open standard switches, retimers, controllers and interface intellectual property that link AI accelerators inside a rack or pod through UALink and scale-up Ethernet, and excluding proprietary fabrics such as NVLink, scale-out networking between racks and the accelerators themselves, is valued at USD 0.2–0.4 billion in 2026 and is projected to reach USD 3.91–7.82 billion by 2034, at a CAGR of 45%.

The 2026 base rests on early revenue from switches, retimers, controllers and interface intellectual property sold for open fabric designs in qualification. Growth then follows the number of accelerator vendors that ship open fabric racks, the size of the scale-up domain per rack and the share of hyperscalers that qualify a second fabric.

The forecast is sensitive to the pace of the first rack scale products, the choice between UALink and Ethernet based fabrics and the response of proprietary fabric suppliers.

Scenarios.

The base case assumes first products in 2026 and 2027 and steady qualification at hyperscalers, bringing the inflection to about 2029 and a 2034 value near the middle of the range. An accelerated case assumes strong demand for supplier choice and a quick release of switch silicon from several vendors, moving the inflection to 2028 and lifting the 2034 value to the top of the range. A delayed case assumes slow switch silicon and a stronger response from proprietary fabrics, moving the inflection to 2031 and holding growth at the bottom of the range.

Growth drivers

• Hyperscaler demand for supplier choice in AI racks.
• Growth in the size of models and scale-up domains.
• Open specifications from UALink and the Open Compute Project.
• Reuse of Ethernet circuits and physical layers.

Enablers

• 224G and 200G signalling technology.
• Interface intellectual property and retimers.
• Switch silicon from Ethernet vendors.
• Rack designs from open hardware programmes.

Restraints and barriers

• Lag behind proprietary bandwidth and software.
• Limited switch silicon in volume.
• Cost and time of qualifying a new fabric.
• Split between UALink and Ethernet based approaches.

The direction of scale-up interconnects is set by hyperscaler demand for supplier choice, the growth in model and rack size, the quality of open specifications, the supply of switch and interface silicon and the readiness of accelerator vendors to adopt open fabrics.

The key participants in scale-up interconnects and the fabric inside AI racks include Advanced Micro Devices, Inc., Broadcom Inc., Intel Corporation, Alphabet Inc., Meta Platforms, Inc., Microsoft Corporation, Amazon Web Services, Inc., Apple Inc., Alibaba Group Holding Limited, Cisco Systems, Inc., Hewlett Packard Enterprise Company, Astera Labs, Inc., Marvell Technology, Inc., NVIDIA Corporation, Synopsys, Inc., Arista Networks, Inc., Credo Technology Group Holding Ltd, Cadence Design Systems, Inc., Dell Technologies Inc., Super Micro Computer, Inc., Qualcomm Incorporated, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Company Limited, Arm Holdings plc, Cerebras Systems Inc., Tenstorrent Inc., Oracle Corporation, CoreWeave, Inc., Lumentum Holdings Inc., Coherent Corp., Corning Incorporated, Amphenol Corporation, TE Connectivity plc, Molex, LLC, Keysight Technologies, Inc., the UALink Consortium, the Open Compute Project Foundation, the Ultra Ethernet Consortium, the IEEE 802.3 working group and the Optical Internetworking Forum.

The brief profiles representative participants in each archetype and assesses which are positioned to lead as open standards compete with proprietary rack fabrics.

Advanced Micro Devices, Inc. leads among accelerator makers shipping open fabric racks, Broadcom Inc., Astera Labs, Inc. and Marvell Technology, Inc. lead among switch, retimer and connectivity silicon suppliers, and Synopsys, Inc. and Cadence Design Systems, Inc. lead among interface intellectual property providers. Competitive intensity is rising as Ethernet switch vendors, retimer specialists and accelerator makers compete for the same slots in rack designs.

Where value migrates.

In 2026 value sits with the proprietary fabric leader and with interface technology providers that serve every standard, while open fabric revenue is small. By 2029 it moves toward switch, retimer and connectivity silicon suppliers and toward accelerator makers that ship open fabric racks, because hyperscalers pay for supplier choice. By 2034 it settles with the suppliers whose silicon and software work across several fabrics, where scale, interoperability and rack level integration carry the margin. Margins hold for silicon suppliers with several accelerator customers and for interface technology providers that serve both UALink and Ethernet, and narrow for suppliers tied to a single accelerator design.

An open specification at rack scale, Ethernet based alternatives, first racks in qualification and hyperscaler demand for supplier choice support growth, while the lag behind proprietary bandwidth and software, limited switch silicon in volume and the cost of qualifying a new fabric hold back the pace.

A strong response from the proprietary leader, delays in switch silicon or a split between UALink and Ethernet approaches could change the pace. The brief therefore tracks four indicators: the number of accelerator vendors with open fabric racks, the share of racks with open fabrics, the size of the scale-up domain per rack and the availability of switch silicon in volume.

Qualification and first racks first, then open fabrics in volume from several vendors, then open and proprietary fabrics side by side is the expected order of change.