Reversible computing Market Outlook 2026–2038: Growth Drivers, Key Companies, Strategic Developments & Adoption Forecast — A Meticulous Next™ Foresight Brief

This Meticulous Next™ brief examines reversible computing, a design approach in which logic circuits recover and reuse the energy of each switching event instead of releasing it as heat. It tests how far energy recovery moves from test chips to licensed blocks inside production processors by 2038, and what that means for chipmakers, design tool suppliers, data centre operators and research agencies that face tightening power limits.

The physical argument is old and the hardware is new. Rolf Landauer showed in 1961 that erasing one bit of information dissipates at least kT ln 2 of energy, and conventional logic erases information at every gate. Vaire Computing, founded in 2021 by Hannah Earley and Rodolfo Rosini after her doctorate at the University of Cambridge, builds resonator circuits that return energy to the supply. The conclusion is that the idea has left theory, and the open question is whether it pays off at the scale of a commercial chip.

Measured silicon now exists. Vaire announced its Ice River test chip on 9 March 2025, built in 22 nanometre CMOS, and reported energy recovery factors of 1.77 for a capacitor array and 1.41 for an adder circuit, above the break-even value of 1.0 and below the 2.0 predicted by simulation. The conclusion is that recovery works on real circuits even after the energy needed to drive the resonator is counted, although the figures come from a small test chip run at 500 MHz.

Research is moving on logic design and tools. A team at the University of California, Davis reported simulations on 10 February 2026 of a combined reversible and irreversible logic operation on superconducting devices at about 16 to 30 kBT, one to two orders of magnitude above the theoretical minimum of 0.347 kBT, and a researcher at Southern Methodist University dated a tool on 15 August 2026 that converts ordinary circuits into energy recovery circuits and lowered modelled energy on most test circuits. The conclusion is that the missing pieces are moving from physics toward design automation, which is the step that lets ordinary chip teams use the method.

The brief treats reversible computing as an emerging signal with a twelve year horizon to 2038. It identifies which chipmakers, design tool suppliers and cloud operators capture value if energy recovery logic becomes a licensed block in production processors. It is a focused 106-page decision brief that presents an indicative trajectory rather than a segmented market model.

Heat comes from throwing energy away. In a conventional gate the charge stored on a wire is dumped to ground each time the signal changes, and the energy is lost as heat. Reversible and adiabatic designs change the signal slowly and return the charge to a resonator, so that much of the energy is reused. The conclusion is that efficiency is gained from how the circuit is driven and not only from smaller transistors.

The theoretical floor is far below present practice. The minimum energy for erasing a bit is kT ln 2, and the University of California, Davis work calculated 0.347 kBT for a partial NAND operation, against 16 to 30 kBT for the simulated protocols. Present CMOS gates operate several orders of magnitude above these levels. The conclusion is that physics leaves very large headroom, and the practical limits come from speed, circuit overhead and resonator losses.

Overhead is the main engineering trade. Energy recovery needs a resonator, clocking that follows its waveform and often more devices per function. The Southern Methodist University tool reported that a circuit with 12.1 percent more devices still used less modelled energy per cycle. The conclusion is that automated synthesis can find designs where the extra devices pay for themselves, and the results are model based and not yet measured on silicon.

Speed and frequency decide where the method fits. Ice River ran at 500 MHz, and Vaire plans a second generation aimed at 1 GHz and the licensing of resonator intellectual property to other chip designers. The conclusion is that the first market is blocks inside larger processors where energy matters more than peak clock speed, and the pace depends on second generation results.

The limits are small test chips, recovery factors below simulation, the complexity of resonator design and the need for tools and standards that ordinary design teams can use. The brief tests each limit against the evidence to 2038.

The reversible computing market, covering test chips, intellectual property licensing, design tools and development services for reversible and adiabatic logic circuits that recover energy instead of discarding it, and excluding conventional low-power CMOS design, quantum computers and academic research funding, is valued at USD 0.005–0.010 billion in 2026 and is projected to reach USD 0.43–0.86 billion by 2038, at a CAGR of 45%.

The 2026 base rests on test chip programmes, early licensing and design service revenue from a very small number of suppliers. Growth then follows the recovery factors reached on larger chips, the maturity of design tools and the willingness of chipmakers to place energy recovery blocks in production designs.

The forecast is sensitive to second generation silicon results, the pace of tool development and the power limits faced by data centre operators.

Scenarios.

The base case assumes second generation chips near 1 GHz with clear recovery gains and the first production blocks around 2032, bringing the inflection to about 2034 and a 2038 value near the middle of the range. An accelerated case assumes strong results on larger chips and early tool support from the leading design software suppliers, moving the inflection to 2032 and lifting the 2038 value to the top of the range. A delayed case assumes that overhead and resonator losses cancel the gains at commercial speeds and that conventional low-power design keeps improving, moving the inflection to 2037 and holding growth at the bottom of the range.

Growth drivers

• Power limits of AI and data centre computing.
• Slowing gains from smaller transistors.
• Measured energy recovery on real silicon.
• Progress in design tools and logic methods.

Enablers

• Standard CMOS manufacturing at mature nodes.
• Resonator and clocking intellectual property.
• Energy aware synthesis and verification tools.
• Academic research on logic and energy limits.

Restraints and barriers

• Recovery factors below simulation on test chips.
• Circuit overhead and resonator losses.
• Limited tool and standard support.
• A small supplier base and early funding.

The direction of reversible computing is set by the power limits of computing, the slowing return from transistor scaling, measured results on silicon, progress in design tools and the readiness of chipmakers to adopt a new circuit style.

The key participants in reversible computing and the energy limit of logic include Intel Corporation, NVIDIA Corporation, Advanced Micro Devices, Inc., Taiwan Semiconductor Manufacturing Company Limited, Samsung Electronics Co., Ltd., GlobalFoundries Inc., Synopsys, Inc., Cadence Design Systems, Inc., Siemens Aktiengesellschaft, International Business Machines Corporation, Alphabet Inc., Microsoft Corporation, Amazon.com, Inc., Arm Holdings plc, Qualcomm Incorporated, Broadcom Inc., Micron Technology, Inc., ASML Holding N.V., Applied Materials, Inc., Lam Research Corporation, Vaire Computing, Meta Platforms, Inc., Oracle Corporation, Hewlett Packard Enterprise Company, Dell Technologies Inc., Marvell Technology, Inc., Texas Instruments Incorporated, STMicroelectronics N.V., Infineon Technologies AG, imec, Sandia National Laboratories, the University of California, Davis, Southern Methodist University, the University of Cambridge, the Massachusetts Institute of Technology, Stanford University, the United States Department of Energy, the Defense Advanced Research Projects Agency and the European Commission.

The brief profiles representative participants in each archetype and assesses which are positioned to lead if energy recovery logic becomes a standard design option.

Vaire Computing leads among start-ups building energy recovery hardware, Synopsys, Inc., Cadence Design Systems, Inc. and Siemens Aktiengesellschaft lead among design tool suppliers, and Intel Corporation, Taiwan Semiconductor Manufacturing Company Limited and Samsung Electronics Co., Ltd. lead among chipmakers and foundries that would manufacture and adopt the blocks. Competitive intensity is very low today and will rise as production blocks arrive.

Where value migrates.

In 2026 value sits with research groups and a few start-ups that sell test chips, licences and design services. By 2032 it moves toward design tool suppliers and foundries that make energy recovery blocks easy to design and manufacture, because chip teams want to use the method without new expertise. By 2038 it settles with the processor designers and suppliers whose chips show lower energy per operation at commercial speeds, where tools, intellectual property and process support carry the margin. Margins hold for suppliers with measured results and tool support, and narrow for suppliers whose overhead cancels the energy gain.

A measured test chip, new tools and logic results, and the power limits of data centres support growth, while recovery below simulation, circuit overhead and a very small supplier base hold back the pace.

Measured results on second generation chips, a leading tool supplier adding support, or a leading chipmaker licensing a block would shift the pace. The brief therefore tracks four indicators: recovery factor at commercial frequency, the number of licensees, the tool support available and the amount of public and private funding.

Test chips and tools first, then production blocks through licensing, then a standard design option for power limited processors is the expected order of change.